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X9C303
Logarithmic Digitally Controlled Potentiometer (XDCPTM)
Data Sheet January 24, 2007 FN8223.1
Terminal Voltage 5V, 100 Taps, Log Taper Description
The Intersil X9C303 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a three-wire interface. The resistor array is composed of 99 resistive elements. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentio-meter or as a two-terminal variable resistor in a wide variety of applications ranging from control, to signal processing, to parameter adjustment. Digitally-controlled potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the use of nonvolatile memory for potentiometer settings retention.
Features
* Solid-state potentiometer * Three-wire serial interface * 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up * 99 resistive elements, log taper - Temperature compensated - End to end resistance, 32k 15% - Terminal voltages, 5V * Low power CMOS - VCC = 5V - Active current, 3mA max. - Standby current, 750A max. * High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years * Packages - 8 Ld TSSOP - 8 Ld SOIC - 8 Ld PDIP
Block Diagram
U/D INC CS 7-Bit Up/Down Counter 99 98 97 7-Bit Nonvolatile Memory 96 One of OneHundred Decoder 2 Store and Recall Control Circuitry 1 0 RL/VL RW/VW RH/VH
Transfer Gates
Resistor Array
VCC VSS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9C303 Ordering Information
PART NUMBER X9C303P X9C303PI X9C303PIZ (Note) X9C303PZ (Note) X9C303S8* X9C303S8I* X9C303S8IZ* (Note) X9C303S8Z* (Note) X9C303V8* X9C303V8I* X9C303V8IZ* (Note) X9C303V8Z* (Note) X9C303S8I-2.7 X9C303S8IZ-2.7 (Note) PART MARKING X9C303P X9C303P I X9C303P ZI X9C303P Z X9C303S X9C303S I X9C303S ZI X9C303S Z 9C303 C303 I C303 IZ 9CC303 Z X9C303S G X9C303S ZG TEMPERATURE RANGE (C) 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 8 Ld PDIP 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld PDIP (300 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) PACKAGE PKG. DWG. # MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 M8.173 M8.173 M8.173 M8.173 MDP0027 MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel.
Pin Descriptions
VH and VL
The high (VH) and low (VL) terminals of the device are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. It should be noted that the terminology of VL and VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.
Pinout
X9C303 (8 LD SOIC, 8 LD TSSOP, 8 LD PDIP) TOP VIEW
(CS) INC (VCC) U/D (INC) VH (U/D) V SS 1 2 3 4 X9C303 8 7 6 5 VCC (VL) CS VL VW (VW) (VSS) (VH)
VW
VW is the wiper terminal, equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40.
Pin Names
SYMBOL VH VW VL VSS VCC U/D INC CS NC DESCRIPTION High Terminal (Potentiometer) Wiper Terminal (Potentiometer) Low Terminal (Potentiometer) Ground Supply Voltage Up/Down Control Input Increment Control Input Chip Select Control Input No Connection
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and whether the counter is incriminated or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the device will be placed in the low power standby mode until the device is selected once again.
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FN8223.1 January 24, 2007
X9C303 Potentiometer Relationships
S100 VH (VS) R99 R98 S99
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of onehundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9C303, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. The wiper movement is performed as described above; once the new position is reached, the system would the keep INC LOW while taking CS HIGH. The new wiper position would be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This would allow the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference: system parameter changes due to temperature drift, etc... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained.
S98 VW
S3 R2
S2 S1
R1 VL
R1 + R2 + . . . + Ri VW G i = 20Log ------------------------------------------------- = --------- ( V L = 0V ) R V TOTAL S R +R +...+R =R 1 2 99 TOTAL (Refer Test Circuit 1)
Principles of Operation
There are three sections of the X9C303: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is reset to the value last stored.
Mode Selection
CS L L H H X L L L INC U/D H L X X X H L Wiper Up Wiper Down Store Wiper Position Standby Current No Store, Return to Standby Wiper Up (not recommended) Wiper Down (not recommended) MODE
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FN8223.1 January 24, 2007
X9C303 Symbol Table
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
Typical Electrical Taper
100.0% 90.0% 80.0% 70.0% % TOTAL RESISTANCE 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93 96 CL 10pF R(VH - VW) R(VW - VL) 99 RL
TAP
Test Circuit #1
VH
Test Circuit #2
VH Test Point
Circuit #3 SPICE Macro Model
RTOTAL RH CH VW Force Current 10pF CW
VS VW VL
Test Point
25pF
VL
RW
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FN8223.1 January 24, 2007
X9C303
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V Voltage on VH and VL Referenced to VSS . . . . . . . . . . . . -8V to +8V V = |VH - VL| X9C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Recommended Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0C to +70C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40C to +85C Military Temperature Range. . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% Power Rating at +25C X9C303 . . . . . . . . . . . . . . . . . . . . . . .10mW Physical Characteristics Marking Includes Manufacturer's Trademark Resistance Value or Code Date Code
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
Over recommended operating conditions unless otherwise specified. LIMITS
SYMBOL RTOTAL
PARAMETER End-to-End Resistance End-to-End Resistance Tolerance
TEST CONDITIONS
MIN
TYP (NOTE 1) 32
MAX
UNIT
-15 -5 -5 Max Wiper Current 1mA Error = log (Vw(n)) - log (Vw(n - 1)) for tap n = 2 - 99, VH-VL = 10V At 1kHz At 2.5MHz T = -40C to +85C Tap position 84 See Circuit 3 0.005 23 20 400 20 10/10/25 40
+15 +5 +5 100 0.115
% V V dB nV(RMS)/ Hz mV(RMS) ppm/C ppm/C pF
VH VL RW
VH Terminal Voltage VL Terminal Voltage Wiper Resistance Tap position relative step size error Resistor Noise Charge Pump Noise End-to-End Resistance Temperature Coefficient Ratiometric Temperature Coefficient
CH/CL/CW (Note 3)
Potentiometer Capacitance
DC Electrical Specifications
Over recommended operating conditions unless otherwise specified. LIMITS
SYMBOL ICC ISB ILI VIH VIL CIN (Note 3)
PARAMETER Vcc Active Current Standby Supply Current CS, INC, U/D Input Leakage Current CS, INC, U/D Input HIGH Voltage CS, INC, U/D Input LOW voltage CS, INC, U/D Input Capacitance
TEST CONDITIONS CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V @ Max tCYC CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS to VCC
MIN
TYP (NOTE 1) 1 200
MAX 3 750 +10
UNIT mA A A V
-10 2
0.8 VCC = 5V, VIN = VSS, TA = +25C, f = 1MHz 10
V pF
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FN8223.1 January 24, 2007
X9C303
DC Electrical Specifications
Over recommended operating conditions unless otherwise specified. (Continued) LIMITS SYMBOL EEPROM SPECS EEPROM Endurance EEPROM Retention Wiper storage operations over recommended operation conditions At +55C 100,000 100 Cycles Years PARAMETER TEST CONDITIONS MIN TYP (NOTE 1) MAX UNIT
Standard Parts
PART NUMBER X9C303 NOTES: 1. Typical values are for TA = +25C and nominal supply voltage. MAXIMUM RESISTANCE 32k WIPER INCREMENTS Log Taper MINIMUM RESISTANCE 40 Typical
A.C. Conditions of Test
Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V Over recommended operating conditions unless otherwise specified. LIMITS SYMBOL tCl tlD tDI tlL tlH tlC tCPH tIW (Note 3) tCYC tR, tF (Note 3) tPU (Note 3) CS to INC Set-up INC HIGH to U/D Change U/D to INC Set-up INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time INC to VW Change INC Cycle Time INC Input Rise and Fall Time Power-up to Wiper Stable 0.2 500 50 2 500 PARAMETER MIN 100 100 2.9 1 1 1 20 100 TYP (Note 2) MAX UNIT ns ns s s s s ms s s ns s mV/s
AC Electrical Specifications
tR VCC (Note 3) VCC Power-up Rate
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FN8223.1 January 24, 2007
X9C303 A.C. Timing
CS tCYC tCI INC tIL tIH tIC tCPH 90% 10% tID tDI tF tR 90%
U/D tIW VW MI
(Note 4)
NOTES: 2. Typical values are for TA = +25C and nominal supply voltage. 3. This parameter is not 100% tested. 4. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
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FN8223.1 January 24, 2007
X9C303 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.116 0.169 0.246 0.0177 8 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.120 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 2.95 4.30 6.25 0.45 8 8o MAX 1.20 0.15 1.05 0.30 0.20 3.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 12/00
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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FN8223.1 January 24, 2007
X9C303 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
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FN8223.1 January 24, 2007
X9C303 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN8223.1 January 24, 2007

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